Keynote Speakers: MECO 2022 & CPSIoT 2022
Letizia Jaccheri
NTNU, Norwegian University of Science and Technology, Department of Computer Science, Faculty of Information Technology and Electrical Engineering
Software for a better society
Currently, software pervades all aspects of society, environment, and human life. The goal of the presented research is to establish new knowledge about opportunities and challenges posed by the rapidly accelerating pace of technological advances and how they impact the economic, political, environmental, social and technological aspects of society. Our research focuses mainly on UN Goals 5 Gender and UN Goal 3 Health. In the lectures I will give a brief history of software engineering and my past research with some examples of ongoing work done in cooperation with the PhD and master students I supervise.
Letizia Jaccheri (Ph.D. from Politecnico di Torino, Italy) is Professor at the Department of Computer Science of the Norwegian University of Science and Technology. Jaccheri’s research is on software engineering at the intersection with gender, children, health. Jaccheri has published more than 200 papers in International conferences and journals. She has been teaching courses in software engineering at various levels since 1994. She has supervised PhD students, Post-doctoral students and acted as opponent for national and international defences. From 2015 to April 2018 she was independent director of Reply S.p.A, an IT company with 10000 employees world wide. She has been general chair of IFIP ICEC 2015, co-chair of ACM IDC 2018, and Program Chair of the European Computer Science Summit 2018. She has participated to several Horizon 2020 projects, among which INITIATE INnovation through bIg daTa and socIal entrepreneurship; UMI Sci-Ed Exploiting Ubiquitous Computing, Mobile Computing and the Internet of Things to promote STEM Education; SOCRATIC SOcial CReATive IntelligenCe Platform for achieving Global Sustainability Goals. She is action chair of COST Action 19122 European Network For Gender Balance in Informatics EUGAIN.
Letizia Jaccheri is passionate about dissemination of computer science and research to the general public and to contribute to recruit female students to computer science and research. In 2021 she won two Norwegian prizes for gender equality in IT.
Luca Benini
Integrated Systems Lab., Dep. Information Technology and Electrical Engineering, ETH Zürich, Switzerland
PULP: Extreme Energy Efficiency for Extreme Edge AI Acceleration
an open platform perspective
The next wave of pervasive AI pushes machine learning (ML) acceleration toward the extreme edge, with mW power budgets, while at the same time it raises the bar in terms of accuracy and capabilities, with new ML models being propose on a daily basis. To succeed in this balancing act, we need principled ways to walk the line between flexible and highly specialized ML acceleration architectures. In this talk I will detail on how to walk the line, drawing from the experience of the open PULP (Parallel Ultra-Low Power) platform, based on ML-enhanced RISC-V processors coupled with domain-specific acceleration engines.
Luca Benini holds the Chair of Digital Circuits and Systems at ETHZ and is Full Professor at the Universita di Bologna. Dr. Benini’s research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He received various awards, including the 2016 IEEE CAS Mac Van Valkenburg award (2016) and the ACM/IEEE A. Richard Newton Award (2020).
Roberto Giorgi
University of Siena, Italy
Extending Performance and Reliability via Modular FPGA Clusters
As the number of transistors per computing system is ever-increasing, so are the fault rates. This issue may be critical also in the area of embedded systems, as they may work in mission-critical conditions and in contexts where they may be subject to several sources of faults.
We propose to provide a further dimension of flexibility by federating the capabilities of several separated FPGA-based independent systems, so as to provide a more resilient system that can also improve the performance by simply joining more systems via an inexpensive and simple high-speed interconnect.
Differently, from traditional checkpointing or lock-stepping, we foresee the possibility of relying on a disciplined data flow among the application threads.
The underlying execution model is known as dataflow-threads (DF-threads) and the fault-detection extension of this model allows to achieve a resilient execution of an application while faults are affecting the system.
In the proposed implementation, the execution time gracefully degrades as the number of faults increases, without the need for global checkpointing and without interrupting the application execution.
The technique has been evaluated on a full-system x86-64 simulator with encouraging results and an FPGA-based implementation is under development.
Roberto Giorgi is an Associate Professor at Dept. of Information Engineering, University of Siena, Italy (qualified for Full Professorship). He received his Ph.D. in Computer Engineering and his MS in Electronics Engineering, Summa cum Laude both from the University of Pisa, Italy. He has been coordinator of a 4-year Future and Emerging Technology European project (TERAFLUX project, 8.5Meuro cost, 2010-2014, 11 partners), coordinator of a 3-year H2020 project (AXIOM, 4Meuro, 2015-2018, 7 partners), Workpackage leader of the Embedded Reconfigurable Architecture project, deputy steering committee member in HiPEAC (High-Performance Embedded-system Architecture and Compiler), participating in SARC (Scalable ARChitectures). He attracted more than 3 Million euros of Research Funding to the University of Siena in the last decade. He took part in ChARM project, developing software for performance evaluation of ARM-processor-based embedded systems with cache memory. He has been IEEE Judge for the IEEE-CSIDC (Computer Society International Design Competition). He led the project “Bluesign Translator”, which received a 5th worldwide prize by IEEE and top companies, and received the FORUM-P.A. prize by the Italian Ministry of Technological and Scientific Innovation, as an absolute winner in the category of “actions for the social integration of disadvantaged people through ICT”. He has been selected by the European Commission as an independent expert for evaluating ICT and HPC European Projects. He is the author of more than 130 scientific papers. His current interests include Computer Architecture themes such as Embedded Systems, Multiprocessors, Memory System Performance, Workload Characterization, Reconfigurable Computing. He is a Lifetime member of ACM and a Senior Member of the IEEE, IEEE
Dimitrios Serphanos
University of Patras and Computer Technology Institute and Press “Diophantus”, Greece
Stavros Koubias
University of Patras and Insustrial Systems Institute, Greece
